The present inventions are related to systems and methods for power management, and more particularly to systems and methods for distributed power utilization and/or switching in a memory system.
Flash memories have been used in a variety of devices where information stored by the device must be maintained even when power is lost to the device. A typical flash memory exhibits a number of cells that can be charged to one of 2N distinct voltage levels representing ‘N’ bits per cell. For example, a two bit cell may be charged to one of four distinct voltage levels each representing a corresponding two bit pattern (i.e., 00, 01, 10, 11). A typical flash memory bank may consist of a number of flash memory devices combined both in parallel and vertically to establish an overall memory size. For example, a number of eight-bit wide by 128K bit deep flash memory devices (i.e., 1M bit memory devices) may be assembled into a 64M bit memory that is sixty-four bits wide and 1M bit deep. In such a memory, sixty-four bit wide words are read/written on each access meaning eight of the flash memory devices are read/written on each access. In some cases, this can result in power management problems.
Hence, for at least the aforementioned reason, there exists a need in the art for advanced systems and methods for implementing memories.